急求一个verilog编写的异步串行通信的程序，最好有校验位，459785950@qq.com。答的好可以再加分

module asyn(clk,rst,wr,wr_bit,addr,bit_in,data_in,t1_ow,rxd,txd,intr,data_out,pcon,scon,rx_**uf);input clk;input rst;input wr;input wr_bit;input [7:0] addr;input bit_in;input [7:0] data_in;input t1_ow;input rxd;output txd;output intr;output [7:0] data_out;output [7:0] scon;output [7:0] pcon;output [7:0] rx_**uf;reg txd;reg [7:0] scon;reg [7:0] pcon;assign intr=scon[1]|scon[0];//wire t1_ow_final;reg div2_flag;reg t1_ow_buf;reg t1_ow_final_buf;// signals with transmit partreg [7:0] tx_**uf;reg send_n; //active low,indicate that it ** transmiting dataswire wr_**uf_en;assign wr_**uf_en=(wr==1'b1&&addr==8'h99);reg wr_**uf_en_mem;wire shift_en;reg [3:0] tx_next_state;reg [3:0] tx_current_state;parameter idle=11,start=0,d0=1,d1=2,d2=3,d3=4,d4=5,d5=6,d6=7,d7=8,tb8_bit=9,stop_bit=10; //states definereg [3:0] osc_cnt;reg [3:0] tx_sample_cnt;reg tx_clk;//signals with receive partreg [3:0] rx_next_state;reg [3:0] rx_current_state;reg [3:0] rx_sample_cnt;wire one_bit;reg rxd_buf;reg [10:0] **uf_rxd_tmp;reg [7:0] rx_**uf;reg sample_7,sample_8,sample_9;reg receive;//signals with both transmiting and receiving parts//always @(*)//begin//sm0=scon[7];//sm1=scon[6];//sm2=scon[5];//ren=scon[4];//tb8=scon[3];//rb8=scon[2];//ti=scon[1];//ri=scon[0];//endalways @(posedge clk or posedge rst) //reg**ter sconbegin if (rst) scon <=8'b0100_0000; else if ((wr) & !(wr_bit) & (addr==8'h98)) scon <=data_in; else if ((wr) & (wr_bit) & (addr[7:3]==5'b10011)) scon[addr[2:0]]<=bit_in; else if (tx_next_state==stop_bit) scon[1] <=1'b1; else case(rx_next_state) start:scon[0]<=1'b0; idle:if(rx_current_state==stop_bit) begin case (scon[7:6]) 2'b00: scon[0] <= 1'b1; 2'b01: if(scon[5]) if(one_bit) scon[0] <= 1'b1; else scon[0] <= 1'b0; else scon[0] <= 1'b1; 2'b10,2'b11: if(scon[5]) scon[0]<=**uf_rxd_tmp[9]; else scon[0]=1'b1; endcase end endcaseend////power control reg**ter//wire smod;assign smod = pcon[7];always @(posedge clk or posedge rst)begin if (rst) pcon <= 8'b0000_0000; else if ((addr==8'h87) & (wr) & !(wr_bit)) pcon <= data_in;endalways @(posedge clk or posedge rst) //osc_cnt if(rst)osc_cnt<=4'b0000;else if(osc_cnt==4'b1011)osc_cnt<=4'b0000;elseosc_cnt<=osc_cnt+1'b1;always @(posedge clk or posedge rst) //t1_ow_buf if(rst)t1_ow_buf<=1'b0;else if(t1_ow)t1_ow_buf<=~t1_ow;always @(posedge clk or posedge rst) //div2_flag if(rst)div2_flag<=1'b0;else if(~t1_ow_buf&t1_ow)div2_flag<=~div2_flag;assign t1_ow_final=(pcon[7]==1'b1)?t1_ow:t1_ow&div2_flag;//transmit partalways @(posedge clk or posedge rst) //t1_ow_final_bufif(rst) t1_ow_final_buf<=1'b0;else t1_ow_final_buf<=t1_ow_final;always @(posedge clk or posedge rst) //tx_sample_cntif(rst)begintx_sample_cnt<=4'b0000;endelse if(t1_ow_final_buf==1'b0&&t1_ow_final==1'b1)tx_sample_cnt<=tx_sample_cnt+1'b1;always @(posedge clk or posedge rst)if(rst)wr_**uf_en_mem<=1'b0;else if (wr_**uf_en&&wr_**uf_en_mem<=1'b0)wr_**uf_en_mem<=1'b1; //represent that the tx_**uf has been loadedelse if(tx_current_state==stop_bit)wr_**uf_en_mem<=1'b0;assign shift_en=wr_**uf_en_mem==1'b1&&tx_sample_cnt==4'b1111&&osc_cnt==4'b1011&&t1_ow_final_buf==1'b0&&t1_ow_final==1'b1;always @(posedge clk or posedge rst)if(rst)tx_**uf<=8'b0000_0000;else if (wr_**uf_en&&wr_**uf_en_mem<=1'b0) tx_**uf<=data_in;else if(send_n==1'b0&&shift_en)tx_**uf<=tx_**uf>>1'b1;//the three always phrase below ** the 3 parts d**cription of state machinealways @(*)//(tx_current_state or wr_**uf_en_mem or tx_sample_cnt or osc_cnt or th1 or tl1 or shift_en)begincase(tx_current_state)idle: if(shift_en) // tx_next_state=start; else tx_next_state= idle;start:if(shift_en) tx_next_state=d0; else tx_next_state=start;d0: if(shift_en) tx_next_state=d1; else tx_next_state=d0;d1: if(shift_en) tx_next_state=d2; else tx_next_state=d1;d2: if(shift_en) tx_next_state=d3; else tx_next_state=d2;d3: if(shift_en) tx_next_state=d4; else tx_next_state=d3;d4: if(shift_en) tx_next_state=d5; else tx_next_state=d4;d5: if(shift_en) tx_next_state=d6; else tx_next_state=d5;d6: if(shift_en) tx_next_state=d7; else tx_next_state=d6;d7: if(shift_en) if(scon[7:6]==2'b00||scon[7:6]==2'b01) tx_next_state=stop_bit; else tx_next_state=tb8_bit; else tx_next_state=d7;tb8_bit: tx_next_state=stop_bit;stop_bit: if(tx_sample_cnt==4'b1111&&osc_cnt==4'b1011&&t1_ow_final==1'b1) tx_next_state=idle; else tx_next_state=stop_bit;default:tx_next_state=idle;endcaseendalways @(posedge clk or posedge rst)if(rst)tx_current_state<=idle;elsetx_current_state<=tx_next_state;always @(posedge clk or posedge rst)if(rst)begintxd<=1'b1;send_n<=1'b1;endelsecase(tx_next_state)idle: begin send_n<=1'b1; txd<=1'b1; endstart:begin send_n<=1'b0; txd<=1'b0; endd0: txd<=tx_**uf[0];d1: txd<=tx_**uf[0];d2: txd<=tx_**uf[0];d3: txd<=tx_**uf[0];d4: txd<=tx_**uf[0];d5: txd<=tx_**uf[0];d6: txd<=tx_**uf[0];d7: txd<=tx_**uf[0];tb8_bit: txd<=scon[3];stop_bit: begin txd<=1'b1; endendcase//receiving partassign rx_shift_en=rx_sample_cnt==4'b1111&&t1_ow_final_buf==1'b0&&t1_ow_final==1'b1;always @(posedge clk or posedge rst) //describe the rxd_bufif(rst)rxd_buf<=1'b0;elserxd_buf<=rxd;always @(posedge clk or posedge rst) //describe the rx_sample_cntif(rst)rx_sample_cnt<=4'b0000;else if(rxd_buf==1'b1&&rxd==1'b0) //此条件启动接收过程rx_sample_cnt<=4'b0000;else if(t1_ow_final)rx_sample_cnt<=rx_sample_cnt+1'b1;always @(posedge clk)if(rx_sample_cnt==4'b0110&&t1_ow_final)sample_7<=rxd;always @(posedge clk)if(rx_sample_cnt==4'b0111&&t1_ow_final)sample_8<=rxd;always @(posedge clk)if(rx_sample_cnt==4'b1000&&t1_ow_final)sample_9<=rxd;assign one_bit=sample_7&&sample_8||sample_7&&sample_9||sample_8&&sample_9;//the three always phrase below ** the 3 parts d**cription of state machinealways @(*)begincase(rx_current_state)idle: if(rxd_buf==1'b1&&rxd==1'b0&&scon[4]==1'b1) //检测到了rxd从1到0的跳变 rx_next_state=start; else rx_next_state= idle;start: if(rx_shift_en) if(~one_bit) rx_next_state=d0; else rx_next_state=idle; else rx_next_state=start;d0: if(rx_shift_en) rx_next_state=d1; else rx_next_state=d0;d1: if(rx_shift_en) rx_next_state=d2; else rx_next_state=d1;d2: if(rx_shift_en) rx_next_state=d3; else rx_next_state=d2;d3: if(rx_shift_en) rx_next_state=d4; else rx_next_state=d3;d4: if(rx_shift_en) rx_next_state=d5; else rx_next_state=d4;d5: if(rx_shift_en) rx_next_state=d6; else rx_next_state=d5;d6: if(rx_shift_en) rx_next_state=d7; else rx_next_state=d6;d7: if(rx_shift_en) if(scon[7:6]==2'b00||scon[7:6]==2'b01) rx_next_state=stop_bit; else rx_next_state=tb8_bit; else rx_next_state=d7;tb8_bit: if(rx_shift_en) rx_next_state=stop_bit; else rx_next_state=tb8_bit; stop_bit: if(rx_shift_en) rx_next_state=idle; else rx_next_state=stop_bit;endcaseendalways @(posedge clk or posedge rst)if(rst)rx_current_state<=idle;elserx_current_state<=rx_next_state;always @(posedge clk or posedge rst)if(rst)receive<=1'b0;elsecase(rx_next_state)idle: receive<=1'b0;start:beginreceive<=1'b1;**uf_rxd_tmp<=10'b11_1111_1111; endd0,d1,d2,d3,d4,d5,d6,d7: if(rx_shift_en) **uf_rxd_tmp<={**uf_rxd_tmp[10:0],one_bit};stop_bit: receive<=1'b1; // end of receivingendcase////serial port buffer (receive)//always @(posedge clk or posedge rst)begin if (rst) rx_**uf<=8'h00; else if (rx_next_state==stop_bit) case (scon[7:6]) 2'b00,2'b01:rx_**uf<=**uf_rxd_tmp[7:0]; 2'b10,2'b11:rx_**uf<=**uf_rxd_tmp[8:1]; endcaseendendmodule 20210311